1. Field of the Invention
The present invention relates to power supply control in a semiconductor circuit.
2. Description of the Related Art
As advances in semiconductor fabrication technology continue to reduce the sizes of transistors, the current that leaks through the transistors in the off-state continues to increase, causing large-scale integrated (LSI) circuits to draw significant amounts of current even in the standby state in which their input signals, output signals, and clock signals are all halted. This is a particularly serious problem for portable devices that operate on battery power; reducing the current consumption of these devices in the standby state has become a major issue. There are various ways to reduce the standby current consumed by an LSI circuit, the most effective of which is to use a switch to shut off its power supply.
Shutting off the power supply of an entire LSI circuit chip presents no particular problem: the same method can be used as is normally used to power the chip on and off. If the power supply of the entire LSI chip cannot be shut off, however, because the chip has an internal clock that must be kept running, for example, then the chip must be divided into two areas: a backup area that is always powered, and a power-off area that is powered on for normal operation and powered off in the standby state.
This requires special design of the circuitry in the boundary region between the backup area and the power-off area. More specifically, when the power supply to the power-off area is switched on or off, during the transient period before the power supply voltage stabilizes, the power-off area may send unintended signals to the backup area or draw unintended current from the backup area. The circuits in the boundary area must be designed to prevent this. A conventional method makes use of an externally generated masking signal.
FIG. 1 shows an example of a semiconductor circuit using this conventional method. The semiconductor circuit comprises an LSI chip and external circuits. The LSI chip includes a logic core 10, an input-output (I/O) section 20, and a real-time clock counter or RTC 30. The external circuits include a signal generator 40, a switch controller 50, a power switch 60, and a power source 70.
The power source 70 supplies power at voltage levels of one and a half volts (1.5 V, VDDRTC) to the RTC 30 and 3.3 V (VDDEX) to the switch controller 50. Both levels are also supplied to the power switch 60, which supplies the 1.5-V level (VDDCORE) to the logic core 10 and the 3.3-V level (VDDIO) to the input-output section 20 and signal generator 40 during normal operation. In the standby state, these power supplies (VDDCORE, VDDIO) are switched off by a control signal from the switch controller 50.
The signal generator 40 generates a reset signal RST and a mask signal MSK.
The logic core 10 includes a central processing unit (CPU) 11 connected by a system bus 12 to a port controller 13 and memory (not shown), a pair of buffers 14 and 15 that receive signals from the input-output section 20 and convert their high logic levels from 3.3 V to 1.5 V, an output buffer 16 and an input buffer 17 through which the system bus 12 is connected to the RTC 30, and a pair of diodes 18 connected to the input terminal of the input buffer 17 for protection from electrostatic discharge (ESD).
The input-output section 20 transfers signals between the LSI chip and external circuits through buffers 21, 22 and ports 23. The buffers 21, 22 transfer the reset signal RST and mask signal MSK to buffers 14, 15 in the logic core 10. The ports 23 are controlled by the port controller 13 for general-purpose use.
The RTC 30 includes an RTC core 31 and an interface 32. The RTC core 31 is connected to an external crystal resonator with which it generates a real-time clock signal CLK having a frequency of substantially thirty-two kilohertz (32 KHz). The RTC core 31 uses this clock signal to count time and stores time information in internal registers (not shown).
The interface 32 receives the level-converted mask signal (msk) from buffer 15 in the logic core 10. A latch 33 comprising an inverter and a NAND gate connected in a loop latches the mask signal, the NAND gate receiving the mask signal and the VDDCORE power supply voltage from the logic core 10 as its two inputs. The latched mask signal is supplied to a synchronizing circuit 34 including a pair of flip-flops (FFs) clocked by the clock signal CLK. The synchronizing circuit 34 removes spike noise from the mask signal, and outputs a synchronous mask signal (mskr) to an AND gate 35. The AND gate 35 is both a buffer and a masking circuit for an input signal I-RTC received from buffer 16 in the logic core 10. The output of AND gate 35 is furnished to the RTC core 31, which returns an output signal O-RTC to the logic core 10. The interface 32 also includes protective diodes 36, 37 through which the I-RTC and O-RTC signal lines are connected to the VDDRTC power supply and ground.
The procedure for powering this semiconductor circuit up can be divided into four steps as follows.
(1) Under control of the switch controller 50, the power switch 60 begins output of the VDDIO and VDDCORE power supplies. The reset signal RST and mask signal MSK remain at the ground level, which is their active level (active low).
(2) After the VDDIO power supply stabilizes, the signal generator 40 inactivates the reset and mask signals by driving them high, and the CPU 11 starts operating. The mask signal (msk) output from the logic core 10 to the RTC 30 goes high.
(3) After a synchronizing delay in the synchronizing circuit 34, the synchronous mask signal (mskr) goes high and the AND gate 35 stops masking input to the RTC core 31.
(4) When necessary, the CPU 11 accesses the RTC core 31 to make settings or obtain time information.
The procedure for powering this semiconductor circuit off can be divided into three steps as follows.
(1) The signal generator 40 drives both the reset signal RST and the mask signal MSK low.
(2) After a propagation delay in the synchronizing circuit 34, the AND gate 35 begins masking input to the RTC core 31.
(3) Under control of the switch controller 50, the power switch 60 halts output of the VDDIO and VDDCORE power supplies. Supply of VDDRTC and VDDEX continues. The fall of VDDCORE locks the latch 33 in the low output state.
Further information can be found in Japanese Patent Application Publications No. 2002-223156 and No. 2002-312073.
The following problems (A) to (E), however, have been observed in the semiconductor circuit described above.
(A) The buffer 22 for the mask signal MSK in the input-output section 20 generally includes a cascaded pair of inverters 22a and 22b, as shown in FIG. 1. The corresponding buffer 15 in the logic core 10 also includes a cascaded pair of inverters 15a and 15b. 
Before power-up, the VDDIO and VDDCORE power supply voltages are both at the ground potential and all of the inputs and outputs of these inverters 22a, 22b, 15a, 15b are low. During power-up, as the power supply levels stabilize over time, the outputs of inverters 15a and 22a should go high while the outputs of inverters 15b and 22b remain low. Since the VDDIO power supply voltage is supplied to the signal generator 40 as well as to the input-output section 20, however, VDDIO rises comparatively slowly. During the transient period before the power supply levels stabilize, due to propagation delay in inverter 22a, for example, there may be a brief interval in which the output level of inverter 22a is low and the output level of inverter 22b goes high, bringing the output level of inverter 15a back to the low level so that inverter 15b drives the mask signal (msk) to the high level. Depending on the timing relation of this interval to the clock signal CLK, the synchronous mask signal (mskr) may go high, allowing the I-RTC signal to propagate through the AND gate 35. The RTC core 31 then receives unpredictable input from the logic core 10 and may malfunction.
(B) When the mask signal MSK is driven low before a power shutoff, the output levels of inverters 22a and 15a go high, and the output levels of inverters 22b and 15b go low, driving the mask signal msk supplied to the RTC 30 low. Next, when power is shut off, the VDDIO and VDDCORE power supply voltages drop to the ground voltage over time, and all of the inputs and outputs of the inverters 22a, 22b, 15a, 15b likewise drop to the low logic level.
Due to capacitance differences, however, the high-to-low transitions of the power supplies and the high-to-low transitions of the signals output by different components of the signal generator 40 do not all take place simultaneously. During the transient period until VDDIO and VDDCORE stabilize at the ground level, there may be a brief period in which the output level of inverter 22a is low, the output level of inverter 22b is high, and the output level of inverter 15a is low, driving the mask signals (msk and mskr) high and allowing unpredictable input signals to reach the RTC core 31, which may then malfunction as in problem (A).
(C) Even if the RTC core 31 does not malfunction, if the mask signal (msk) goes high while the VDDCORE power supply voltage is still above the switching threshold of the NAND gate in the latch 33, the latch 33 may begin to supply the VDDRTC power supply voltage to the logic core 10 through buffer 15. The VDDRTC potential may then return from the logic core to the NAND gate on the VDDCORE signal line, causing the latch 33 to remain in the high output state even after VDDCORE has fallen to the ground potential. The logic core 10 then fails to power down completely and continues to draw leakage current through buffer 15 in the standby state. Moreover, the I-RTC signal line is left unmasked, so the RTC core 31 will be exposed to further unpredictable input the next time the logic core 10 is powered up.
(D) Although the low-to-high transition of the synchronous mask signal (mskr) is synchronized with the RTC clock signal CLK, this clock signal CLK is not synchronized with the bus clock (not shown) by which the CPU 11 accesses the RTC 30, so the CPU 11 cannot tell exactly when the internal mask in the RTC 30 has been cleared. When power is switched on, the CPU 11 may attempt to write data in these registers before the mask is cleared and then operate on the assumption that the data have been duly written, when in fact the data have been blocked by AND gate 35. Furthermore, if the latch 33 or synchronizing circuit 34 fails to respond promptly to the high-to-low transition of the mask signal (msk), power may be shut off while the I-RTC signal is still unmasked, allowing unpredictable input to reach the RTC core 31.
(E) When VDDCORE power is shut off, the O-RTC signal output from the backup area has to be driven low. This is inconvenient, but if power is shut off while O-RTC is high, the protective diode 18 on the VDDCORE side of the O-RTC signal line becomes forward biased and conducts current from the backup area into the logic core 10. The logic core 10 then fails to power down completely and continues to draw leakage current in the standby state.
This problem cannot be solved by moving the O-RTC protective diodes 18 into the backup area, because the protective diodes must be placed near the input of the buffer 17 they protect.